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hm6264bi series 64k sram (8-kword 8-bit) wide temperature range version ade-203-492c (z) rev. 3.0 may. 8, 2000 description the hitachi hm6264bi is 64k-bit static ram organized 8-kword 8-bit. it realizes higher performance and low power consumption by 1.5 m m cmos process technology. the device, packaged in 450 mil sop (foot print pitch width), 600 mil plastic dip, is available for high density mounting. features single 5 v supply: 5 v 10% access time: 100/120 ns (max) power dissipation: ? standby: 10 m w (typ) ? operation: 15 mw (typ) (f = 1 mhz) completely static memory ? no clock or timing strobe required equal access and cycle times common data input and output ? three state output directly ttl compatible ? all inputs and outputs battery backup operation capability operating temperature range: ?0?c to +85?c
hm6264bi series 2 ordering information type no. access time package hm6264blpi-10 hm6264blpi-12 100 ns 120 ns 600-mil, 28-pin plastic dip (dp-28) hm6264blfpi-10t hm6264blfpi-12t 100 ns 120 ns 450-mil, 28-pin plastic sop(fp-28da) pin arrangement we i/o2 27 1 nc 2 a12 3 a7 4 a6 5 a5 6 a4 7 a3 8 a2 9 a1 10 a0 11 i/o1 12 13 14 v ss i/o3 v cc 28 cs2 26 a8 25 a9 24 a11 23 22 a10 21 cs1 20 i/o8 19 i/o7 18 i/o6 17 i/o5 16 i/o4 15 (top view) oe hm6264blpi/blfpi series
hm6264bi series 3 pin description pin name function a0 to a12 address input i/o1 to i/o8 data input/output cs1 chip select 1 cs2 chip select 2 we write enable oe output enable nc no connection v cc power supply v ss ground block diagram v cc v ss memory array 256 256 row decoder a11 a8 a9 a7 a12 a5 a6 a4 column i/o column decoder input data control a1 a3 timing pulse generator read, write control i/o1 i/o8 cs2 cs1 we oe a2 a0 a10
hm6264bi series 4 function table we cs1 cs2 oe mode v cc current i/o pin ref. cycle h not selected (power down) i sb , i sb1 high-z l not selected (power down) i sb , i sb1 high-z h l h h output disable i cc high-z h l h l read i cc dout read cycle (1)?3) l l h h write i cc din write cycle (1) l l h l write i cc din write cycle (2) note: : h or l absolute maximum ratings parameter symbol value unit power supply voltage* 1 v cc ?.5 to +7.0 v terminal voltage* 1 v t ?.5* 2 to v cc + 0.3* 3 v power dissipation p t 1.0 w operating temperature topr ?0 to +85 c storage temperature tstg ?5 to +125 c storage temperature under bias tbias ?0 to +85 c notes: 1. relative to v ss 2. v t min: ?.0 v for pulse half-width 50 ns 3. maximum voltage is 7.0 v recommended dc operating conditions (ta = ?0 to +85 c) parameter symbol min typ max unit supply voltage v cc 4.5 5.0 5.5 v v ss 000v input high voltage v ih 2.4 v cc + 0.3 v input low voltage v il ?.3* 1 0.6 v note: 1. v il min: ?.0 v for pulse half-width 50 ns
hm6264bi series 5 dc characteristics (ta = ?0 to +85 c, v cc = 5 v 10%, v ss = 0 v) parameter symbol min typ* 1 max unit test conditions input leakage current |i li | 2 m a vin = v ss to v cc output leakage current |i lo | 2 m a cs1 = v ih or cs2 = v il or oe = v ih or we = v il , v i/o = v ss to v cc operating power supply current i ccdc 7 20 ma cs1 = v il , cs2 = v ih , i i/o = 0 ma others = v ih /v il average operating power supply current i cc1 30 50 ma min cycle, duty = 100%, cs1 = v il , cs2 = v ih , i i/o = 0 ma others = v ih /v il i cc2 3 8 ma cycle time = 1 m s, duty = 100%, i i/o = 0 ma cs1 0.2 v, cs2 3 v cc ?0.2 v, v ih 3 v cc ?0.2 v, v il 0.2 v standby power supply current i sb 13ma cs1 = v ih , cs2 = v il i sb1 * 2 2 200 m a cs1 3 v cc ?0.2 v, cs2 3 v cc ?0.2 v or 0 v cs2 0.2 v, 0 v vin output low voltage v ol 0.4 v i ol = 2.1 ma output high voltage v oh 2.4 v i oh = ?.0 ma notes: 1. typical values are at v cc = 5.0 v, ta = +25 c and not guaranteed. 2. v il min = ?.3v capacitance (ta = 25 c, f = 1.0 mhz) parameter symbol min typ max unit test conditions input capacitance* 1 cin 5 pf vin = 0 v input/output capacitance* 1 c i/o 7 pfv i/o = 0 v note: 1. this parameter is sampled and not 100% tested.
hm6264bi series 6 ac characteristics (ta = ?0 to +85 c, v cc = 5 v 10%, unless otherwise noted.) test conditions input pulse levels: 0.6 v to 2.4 v input and output timing reference level: 1.5 v input rise and fall time: 10 ns output load: 1 ttl gate + c l (100 pf) (including scope & jig) read cycle hm6264bi-10 hm6264bi-12 parameter symbol min max min max unit notes read cycle time t rc 100 120 ns address access time t aa 100 120 ns chip select access time cs1 t co1 100 120 ns cs2 t co2 100 120 ns output enable to output valid t oe 50 60 ns chip selection to output in low-z cs1 t lz1 10 10 ns 2 cs2 t lz2 10 10 ns 2 output enable to output in low-z t olz 55ns2 chip deselection in to output in high-z cs1 t hz1 0 35 0 40 ns 1, 2 cs2 t hz2 0 35 0 40 ns 1, 2 output disable to output in high-z t ohz 0 35 0 40 ns 1, 2 output hold from address change t oh 10 10 ns notes: 1. t hz is defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. at any given temperature and voltage condition, t hz maximum is less than t lz minimum both for a given device and from device to device. 3. address must be valid prior to or simultaneously with cs1 going low or cs2 going high.
hm6264bi series 7 read timing waveform (1) ( we = v ih ) t rc t aa t co1 t co2 t lz1 t hz1 t hz2 t lz2 t oe t olz t ohz t oh address cs1 cs2 dout oe valid address valid data high impedance read timing waveform (2) ( we = v ih , oe = v il ) t aa address dout t oh valid address valid data t oh
hm6264bi series 8 read timing waveform (3) ( we = v ih , oe = v il )* 3 cs1 cs2 dout valid data co1 t lz1 t lz2 co2 t hz1 t hz2 t t
hm6264bi series 9 write cycle hm6264bi-10 hm6264bi-12 parameter symbol min max min max unit notes write cycle time t wc 100 120 ns chip selection to end of write t cw 80 85 ns 2 address setup time t as 00ns3 address valid to end of write t aw 80 85 ns write pulse width t wp 60 70 ns 1, 9 write recovery time t wr 00ns4 we to output in high-z t whz 0 35 0 40 ns 5 data to write time overlap t dw 40 40 ns data hold from write time t dh 00ns output active from end of write t ow 55ns output disable to output in high-z t ohz 0 35 0 40 ns 5 notes: 1. a write occurs during the overlap of a low cs1 , and high cs2, and a high we . a write begins at the latest transition among cs1 going low,cs2 going high and we going low. a write ends at the earliest transition among cs1 going high cs2 going low and we going high. time t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the later of cs1 going low or cs2 going high to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the earliest of cs1 or we going high or cs2 going low to the end of write cycle. 5. during this period, i/o pins are in the output state, therefore the input signals of the opposite phase to the outputs must not be applied. 6. if cs1 goes low simultaneously with we going low after we goes low, the outputs remain in high impedance state. 7. dout is the same phase of the written data in this write cycle. 8. dout is the read data of the next address 9. in the write cycle with oe low fixed, t wp must satisfy the following equation to avoid a problem of data bus contention t wp 3 t whz max + t dw min.
hm6264bi series 10 write timing waveform (1) ( oe clock) t wc t cw *1 t aw t wp t ohz t dw t dh address oe cs1 we cs2 dout din t wr t as valid address valid data high impedance high impedance
hm6264bi series 11 write timing waveform (2) ( oe low fixed) ( oe = v il ) t wc t aw t cw t wp t as t whz t oh t ow *2 *1 *3 t dh t dw *4 address cs1 cs2 dout din we t wr valid data valid address high impedance
hm6264bi series 12 low v cc data retention characteristics (ta = ?0 to +85 c) parameter symbol min typ* 1 max unit test conditions* 3 v cc for data retention v dr 2.0 v cs1 3 v cc ?.2 v, cs2 3 v cc ?.2 v or cs2 0.2 v vin 3 0 v data retention current i ccdr ?* 1 100* 2 m av cc = 3.0 v, 0 v vin v cc cs1 3 v cc ?.2 v, cs2 3 v cc ?.2 v or 0 v cs2 0.2 v chip deselect to data retention time t cdr 0 ns see retention waveform operation recovery time t r 5 ms notes: 1. reference data at ta = 25 c. 2. 10 m a max at ta = ?0 to + 40 c. 3. cs2 controls address buffer, we buffer, cs1 buffer, oe buffer, and din buffer. if cs2 controls data retention mode, vin levels (address, we , oe , cs1 , i/o) can be in the high impedance state. if cs1 controls data retention mode, cs2 must be cs2 3 v cc ?0.2 v or 0 v cs2 0.2 v. the other input levels (address, we , oe , i/o) can be in the high impedance state.
hm6264bi series 13 low v cc data retention timing waveform (1) ( cs1 controlled) v cc 4.5 v 2.4 v 0 v cs1 t cdr t r cs1 3 v cc ?0.2 v v dr data retention mode low v cc data retention timing waveform (2) (cs2 controlled) v cc 4.5 v 0 v cs2 t r v dr data retention mode 0.6 v t cdr 0 v cs2 0.2 v
hm6264bi series 14 package dimensions hm6264blpi series (dp-28) hitachi code jedec eiaj weight (reference value) dp-28 conforms 4.6 g unit: mm 0.51 min 2.54 min 0.25 + 0.11 ?0.05 2.54 0.25 0.48 0.10 0 ?15 15.24 1.2 35.6 36.5 max 13.4 14.6 max 1 14 15 28 5.70 max 1.9 max
hm6264bi series 15 package dimensions (cont.) hm6264blfpi series (fp-28da) hitachi code jedec eiaj weight (reference value) fp-28da conforms conforms 0.82 g unit: mm *dimension including the plating thickness base material dimension *0.17 0.05 3.00 max 8.40 18.00 18.75 max 1.12 max 28 15 1 14 11.80 0.30 0 ?8 1.00 0.20 1.70 0.20 0.15 m *0.40 0.08 1.27 0.38 0.06 + 0.15 ?0.10 0.20 0.15 0.04
hm6264bi series 16 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/index.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:
hm6264bi series 17 revision record rev. date contents of modification drawn by approved by 0.0 dec. 1, 1995 initial issue i. ogiwara k. yoshizaki 1.0 sep. 5, 1996 deletion of preliminary i. ogiwara k. imato 2.0 feb. 9, 1998 change of subtitle change of fp-28da i. ogiwara k. imato 3.0 may. 8, 2000 low v cc data retention characteristics note 2: v il min = - 0.3 v to 10 m a max at ta = ?0 to + 40 c

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